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IDT79RV4640/IDT79RC64V474 PCI MEZZANINE CARD
FEATURES:
* PCI Mezzanine Card (PMC) (IEEE 1386) form factor * 7M9510 High performance IDT79RV4640 MIPS Processor - 100Mhz, 150Mhz, 180Mhz, 200MHz CPU speeds supported - 50MHz maximum CPU bus frequency - 33MHz maximum PCI bus frequency * 7M9514 High performance IDT79RC64V474 MIPS Processor - 180Mhz, 200Mhz, 250Mhz CPU speeds supported - 50MHz maximum CPU bus frequency - 33MHz maximum PCI bus frequency * DRAM - 72-position SIMM slot - 4MB to 128MB of DRAM supported - 32-bit width * Flash - 2MB of on board Flash memory - 32-bit width * EPROM - up to 512KB - 8-bit width - 32 Pin PLCC socket * Two serial interface ports (16550A compatible) * Uses Galileo GT-64011 PCI System controller - DMA - four independent channels - chaining via linked lists of records - byte alignment on source and destination - transfers through a 32 byte internal FIFO which moves data between PCI, memory and devices
PRELIMINARY IDT7M9510 IDT7M9514
PCI - host to PCI bridge - PCI to main memory bridge - fully compatible to PCI rev 2.1 - high performance PCI interfaces via 96 bytes of posted write and read prefetch buffers * Other Features - Manual Cold Reset (Pushbutton and two pin header) - hardware based masking of interrupts - Configurable Timer Interrupt Generator - 32 Bits of user defined I/O mapped through system FPGA - VxWorks Board Support Package available from IDT
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DESCRIPTION:
The IDT7M9510/7M9514 is a Single Board Computer utilizing IDT's 79RV4640/79RC64V474 MIPS processor. This CPU Mezzanine Card is designed for use in applications where low profile, parallel board to board mounting is required. The 7M9510/7M9514 consists of an IDT79RV4640 / IDT79RC64V474 processor based subsystem that can either form the core CPU function for an embedded application, or can be an optional add-in accelerator to a PCI based system through a PCI v2.1 compatible, PMC Standard (IEEE P1386.1) connector. The card conforms, in length and width to the standard single size PMC form factor as specified in IEEE P1386.1, and it contains all the features required of a typical CPU subsystem for embedded processor applications. Some of these features include: DRAM, Flash, serial ports and full PCI interrupt support.
FUNCTIONAL BLOCK DIAGRAM
EPR OM
8
Device Bus
PM C User I/O Header
32
Flash
32
Watch Dog Timer ID T RV4640/ RC64V474
Serial connector SIO Serial connector
System FPGA
DR AM
32
CPU Bus
GT-64011
32
33Mhz PCI Bus
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March 1999
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(c) 1999 Integrated Device Technology, Inc.
IDT7M9510 / IDT7M9514
IDT
BOARD OVERVIEW
The IDT7M9510/9514 consists of the following functional blocks: IDT79RV4640/IDT79RC64V474 MIPS processor, Galileo GT-64011 PCI System Controller, DRAM memory, system Glue Logic (FPGA based), Flash/ EPROM and dual serial channels. The IDT7M9510/9514 CPU subsystem is designed to interface with its targeted system through a standard PCI Mezzanine Card form factor.
SYSTEM FPGA
The system FPGA is responsible for the following functions: Processor initialization, Reset Control, Device Decoding, Interrupt Masking / Mapping.
PROCESSOR INITIALIZATION
The 79RV4640 / 79RC64V474 requires a serial data stream for initialization. The initialization process is handled by the system FPGA.
IDT79RV4640 PROCESSOR
The IDT79RV4640 is a high performance cost-effective MIPS processor targeted at embedded applications which runs at internal frequencies from 100MHz to 200MHz. Further information can be found in the 79RV4640 Data Sheet, available from IDT.
RESET CONTROL
Once the FPGA is loaded, the CPU is booted by sequencing the VCCOK, WARMRESET, COLDRESET lines. At boot-up, the CPU applies MODECLOCK to the FPGA to read out several bytes of configuration information using the MODEIN line. There is a push button for resetting the 7M9510 / 7M9514. This is connected to the FPGA through the SYSRESET signal. Additionally, a 2-pin header is provided for connection to an external reset switch.
IDT79RC64V474 PROCESSOR
The IDT79RC64V474 is a high performance cost-effective MIPS processor targeted at embedded applications which runs at internal frequencies from 180MHz to 250MHz. Further information can be found in the 79RC64V474 Data Sheet, available from IDT.
INTERRUPT STRUCTURE
The system FPGA implements a basic interrupt controller that maps the various interrupt sources to the CPU interrupts. It also gives the CPU the ability to mask interrupts and generate PCI interrupts.
GT-64011 PCI SYSTEM CONTROLLER
The GT-64011 is a system support device from Galileo Technology, Inc. This chip provides the bulk of the system control and support functions required for a MIPS RV4640/RC64V474 CPU based system. The GT-64011 has a three bus architecture. These three busses are: a CPU bus interface, a PCI bus interface and a memory/device bus interface. In addition the GT-64011 contains a DRAM controller and a DMA controller. Further information can be found in the GT-64011 Data Sheet, available from Galileo Technology.
PCI INTERFACE
The GT-64011 includes a full featured host to PCI bridge which can operate as either a target or initiator. For improved performance the bridge contains 96 bytes of posted write and read prefetch buffers. The GT-64011 initiates PCI cycles when either the CPU or the DMA engine generates a bus cycle to PCI address space. These cycles can be either Memory, Interrupt Acknowledge, Special, I/O, or Configuration cycles. Configuration registers can be accessed from either the host bus or the PCI bus. The GT-64011 includes a full featured DRAM controller and generates all control signals for the DRAM SIMM. Further information can be found in the GT-64011 Data Sheet, available from Galileo Technology.
DRAM
The main memory is implemented using one standard 72-position DRAM SIMM providing a 32-bit path to memory. The main memory is designed to support one or two banks of DRAM which is dependent on the type of SIMM being used. One bank is supported when a single bank DRAM SIMM is used (e.g., 1M x 32), and two banks are supported when a double bank DRAM SIMM is used (e.g., 2M x 32). The design can use any standard DRAM SIMM containing 4MB (1M x 32), 8MB (2M x 32), 16 MB (4M x 32), or 32MB (8M x 32), 64MB (16M x 32), or 128MB (32M x 32) allowing the 7M9510/7M9514 to have up to a maximum of 128MB of memory. 60ns memory is recommended. The memory configuration is flexible and is field upgradeable.
PC16552 DUAL SERIAL PORT CONTROLLER
The PC16552D is a Dual Universal Asynchronous Receiver/Transmitter. Each independent channel is software compatible with the PC16550D. Further information can be found in the PC16552D Data Sheet, available from National Semiconductor.
BOOT EPROM
The Boot EPROM is a standard 512K x 8 EPROM which holds the boot code, the debug monitor and power-on diagnostics. (Socket supports Flash chip for development)
WATCHDOG TIMER
The WatchDog Timer generates a non-maskable interrupt from a MAX706TCSA. It is used to control the system reset logic and to provide a watchdog reset. Further information can be found in the MAX706 Data Sheet, available from Maxim.
FLASH MEMORY
The 7M9510 / 7M9514 has 2MB of Flash on board, configured as 512K x 32.
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(c) 1999 Integrated Device Technology, Inc.
IDT7M9510 / IDT7M9514
IDT
SERIAL PORTS
There are two RS232-C serial port connectors on the 7M9510 / 7M9514 which are labeled on the board as "COM1" and "COM2". The Pin #1 reference marking on the PCB should be utilized to ensure proper orientation when connecting adapter cables to the header.
SERIAL HEADER PINOUT (COM1, COM2)
(Top View) DCD RD TD DTR GND 1 3 5 7 9 2 DSR 4 RTS 6 CTS 8 RI 10 NC
SOFTWARE MEMORY MAP
The following is the default memory map of the IDT7M9510 / 7M9514. These values can be changed by writing to the appropriate address decode registers in the GT-64011. For further information on reconfiguring the Memory Map refer to the GT-64011 Data Sheet, available from Galileo Technology.
GT-64011 Physical Address 0x0000 0000 0x0080 0000 0x1000 0000 0x1200 0000 0x1400 0000 0x1FC0 0000 0x1C80 0000 0x1C20 0BE0 0x1C20 0FE0 0xF200 0000 Size 8MB 8MB ------------4MB 2MB ------------Description DRAM Bank 0 DRAM Bank 1 PCI I/O PCI Me mo ry 0 GT64011 Inte rnal Re g iste rs Bo o t EPROM Flash Me mo ry Se rial Po rt - COM1 Se rial Po rt - COM2 PC1 Me mo ry 1
Device Select --------------------Bo o tCS CS1 CS0 CS0 ----4095 tbl 01
POWER REQUIREMENTS
7M9510S180M Mi n Vc c 5 Vc c 3 Icc5 Icc3 4.75V 3.15V --------Max 5.25V 3.45V TBD TBD 7M9510S150M Mi n 4.75V 3.15V --------Max 5.25V 3.45V TBD TBD
7M9510S100M Mi n 4.75V 3.15V --------Max 5.25V 3.45V TBD TBD
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ENVIRONMENTAL
Temp. (C) Condition Op e rating Und e r Bias Sto rag e Mi n 0 -10 -25 Max 50 50 60 Humidity (1) Mi n 20% 10% 10% Max 80% 90% 90% Altitude Mi n 0 0 0 Max 10,000 10,000
Notes: 1. Non-Condensing
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(c) 1999 Integrated Device Technology, Inc.
IDT7M9510 / IDT7M9514
IDT
BOARD DIMENSIONS
TO P V IE W B O T TO M V IE W
74.127 73.873
.
RESET
. PN4 PN2 PN1 FPGA
GT-64011
FLASH 512Kx8 DRAM SIMM SCKT
PLL
FLASH 512Kx8
149.127 148.873
FLASH 512Kx8
CONFIG EPROM
BOOT EPROM
FLASH 512Kx8
DUART
Pin 1
COM1
Pin 1
COM2
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NOTES: 1. All dimensions in millimeters (mm).
SIDE VIEW
M ax Com ponent Height Top 14.278 14.024 6.178 5.924 M ax Com ponent Height Bottom
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(c) 1999 Integrated Device Technology, Inc.
XTAL
RV4640/ RC64V474
IDT7M9510 / IDT7M9514
IDT
PMC CONNECTORS
The 7M9510 / 7M9514 utilizes three 64 position connectors that are compliant with the PMC standard. The placement of these connectors is in compliance with the Common Mezzanine Card (CMC) Specification (IEEE 1386) and the PCI Mezzanine Card (PMC) Specification (IEEE 1386.1). Headers correspond as follows: -J1 on the 7M9510 / 7M9514 corresponds to PN11 (PN1) and P12 (PN2) in the PMC and CMC Specifications. -J2 on the 7M9510 / 7M9514 corresponds to P14 (PN4) in the PMC and CMC Specifications. For further information on the mechanical placement of the PMC headers, refer to the Common Mezzanine Card (CMC) Specification (IEEE 1386).
PIN ASSIGNMENTS
The 32-bit bus is implemented in J1 (PN1 and PN2), in compliance with the PMC Specifications and is provided below. The User-Defined I/O is implemented in J2 (PN4) and is provided below.
PN1
P in # Sig nal Name Sig nal Name 1 TCK -12V (1) 3 GND INTA# 5 INTB# INTC# 7 BUSMODEE1# +5v 9 INTD# PCI-RSVD (1) 11 GND PCI-RSVD (1) 13 CLK GND 15 GND GNT# 17 REQ# +5V 19 V(I/O) (1) AD[31] 21 AD[28] AD[27] 23 AD[25] GND 25 GND C/BE[3]# 27 AD[22] AD[21] 29 AD[19] +5V 31 V(I/O) (1) AD[17] 33 FRAME# GND 35 GND IRDY# 37 DEVSEL# +5V 39 GND LOCK# 41 SDONE# ( (1) SBO# (1) 43 PAR GND (1) 45 V(I/O) AD[15] 47 AD[12] AD[11] 49 AD[09] +5V 51 GND C/BE[0]# 53 AD[06] AD[05] 55 AD[04] GND 57 V(I/O) AD[13] 59 AD[02] AD[01] 61 AD[00] +5V 63 GND REQ64# NOTES: 1. Not connected on 7M9510 / 7M9514 P in # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
4095 tbl 04
PN2
P in # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 Sig nal Name +12V (1) TMS TDI GND PCI-RSVD (1) BUSMODE2# (1) RST# +3.3V PCI-RSVD (1) AD[30] GND AD[24] IDSEL +3.3V AD]18] AD[16] GND TRDY# GND PERR# +3.3V C/BE[1]# AD[14] GND AD[08] AD[07] +3.3V PMC-RSVD (1) PMC-RSVD (1) GND ACK64# (1) GND Sig nal Name TRST# TDO GND PCI-RSVD (1) PCI-RSVD (1) +3.3V BUSMODE3# BUSMODE4# GND AD[29] AD[26] +3.3V AD[23] AD[20] GND C/BE[2]# PMC-RSVD (1) +3.3V STOP# GND SERR# GND AD[13] AD[10] +3.3V PMC-RSVD (1) PMC-RSVD (1) GND PMC-RSVD (1) PMC-RSVD (1) +3.3V PMC-RSVD (1) P in # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
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(c) 1999 Integrated Device Technology, Inc.
IDT7M9510 / IDT7M9514
IDT
PN4 (1)
P in # 1 3 5 7 9 11 13 15 17 18 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 Sig nal Name USER I/O # 1 USER I/O # 3 USER I/O # 5 USER I/O # 7 USER I/O # 9 USER I/O # 11 USER I/O # 13 NC NC NC USER I/O # 21 USER I/O # 23 NC USER I/O # 27 USER I/O # 29 NC USER I/O # 33 NC NC NC NC NC NC NC NC NC NC NC USER I/O # 57 USER I/O # 59 USER I/O # 61 USER I/O # 63 Sig nal Name NC NC USER I/O # 6 USER I/O # 8 USER I/O # 10 USER I/O # 12 USER I/O # 14 USER I/O # 16 NC NC USER I/O # 22 USER I/O # 24 USER I/O # 26 USER I/O # 28 USER I/O # 30 NC USER I/O # 34 NC NC NC NC NC NC NC NC NC NC NC USER I/O # 58 USER I/O # 60 USER I/O # 62 USER I/O # 64 P in # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
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7M9510SR Version
The "SR" version of the 7M9510 is intended for customers using the I-Cube RaptorTM Fast Ethernet Switch Design. In this configuration, the Boot ROM shipped with the 7M9510 contains the most recent version of the I-Cube "MiniBoot Monitor" (MBM). For applications other than the I-Cube RaptorTM Reference Design and the I-Cube FPGA configuration PROM, the recommended board configuration is the 7M9510SE which ships with IDT/Sim and IDT FPGA configuration PROM.
7M9510SE Version (EVALUATION)
The "SE" version of the 7M9510 is packaged to support software development and prototyping. Currently the Evaluation package contains the following material: - 1 7M9510S - 1 8MB (2M x 32) EDO DRAM SIMM - 1 512KB (512K x 8) IDT/Sim Boot ROM Alternately, the 7M9710 Development Kit may be ordered. This kit includes all of the 7M9510SE components listed above. In addition the 7M9710 includes the following items: - 1 set of 7M9510 board schematics - 1 copy of 7M9510 Datasheet - 2 10 pin Serial Port to DB9 Adapter Cables - 2 6 foot DB9 to DB9 null modem serial cables - 1 7M9502 PCI Backplane - 1 7M9710 Quickstart Guide
NOTES: 1. All of the User I/O pins are mapped through the on board FPGA.
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(c) 1999 Integrated Device Technology, Inc.
ORDERING INFORMATION
IDT XXXXX Device Type X Power X Speed X Package X Process/ Tem perature Range Blank Comm ercial (0 o C to +70 o C)
M
PM C-Standard PCI Connection Processor Core Frequency (MHz) 7M 95 14 O nly
250 } 200 180 150 100 S SE SR
}
7M 95 10 O nly Standard Configuration (2M B Flash/0M B DRAM) Evaluation Configuration (2MB Flash/8M B DRAM ) I-C ube Raptor Version IDT79RV4640 Processor-based card IDT79RC64V474 Processor-based card
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7M9510 7M9514
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 fax: 408-492-8674 www.idt.com
for Tech Support: 408-988-5647 ssdhelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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